Research thrust I: Design of energy harvesting systems for industrial IoT sensing
Collaborators: Yuechen Yang, Abraham Shin, Advisors: Prof. Jeffrey Lang, Prof. Anantha Chandrakasan
|MEMS harvester sensor||Low power management IC|
Project description: The goals of the project is to design a complete integrated energy harvesting solution for machine health monitoring. It involves the co-design of (i) Lorentz force based MEMS harvester and (ii) a low power startup circuit, and voltage regulator IC design.
Vibration-based machine health monitoring provides an efficient method of tracking real-time performance of machines to enable predictive maintenance and avoid machine down-time. Sensors are attached to the vibrating parts that can periodically transmit data indicative of machine health. The key challenges of designing such systems are: building sensors that can operate at low powers of vibration signals, tolerance to manufacturing variations, small form-factor, designing low-power electronics for battery-less operation, and efficient power extraction.
Harvester: A Lorentz force based MEMS energy harvesting system is built in this work that can extract ~400 uW from machine vibrations around 50 Hz with external acceleration in the range of 0.2-1 g. The harvester consists of a spring-mass system fabricated using standard Si-MEMS process that oscillates under external vibrations. Magnets embedded in the mass create time varying magnetic flux during their translational motion. Voltage is induced in the windings placed above and below the plane of motion of the spring-mass system in accordance with Lorentz force principle. The harvester is designed to have a matched translational resonance frequency of 50 Hz to maximize power extraction, with higher alternate resonant modes. The geometry parameters are optimized to achieve a power output of 400 uW, while retaining compactness and mechanical stability.
Power management IC: The associated power electronics is co-designed with the harvester to deliver 300 uW to the load at 1.8 V regulated output voltage. A boost converter based on H-bridge topology is adopted to perform impedance tuning and reactive power conditioning for maximizing power extraction under 5% variation in harvester-resonant frequency due to manufacturing tolerances. The circuitry also achieves cold-start up using Meissner-oscillator topology that can start from low voltages of ~100 mV under 5% off-resonance conditions. The integrated circuit implemented in TSMC 180-nm platform can be co-packaged with the harvester and forms a compact energy harvesting system solution for machine health monitoring.
The work has resulted in demonstration of record power density vibration energy harvesters (10x state-of-art) and low-power conditioning IC that accomplishes record low voltage AC input cold-start and harvester's frequency tuning capability.
Research thrust II: III-V+ CMOS hetero-integration for next-generation smart vehicular RF-communication
Collaborators: Dr. Pilsoon Choi- MIT, Dr. Sameer Joglekar, Dr. Chiah Siau Ben- NTU, Dr. Liu Zhihong- MIT
i) RF-device design for RF-system performance: High linearity nanofin GaN-HEMTs for low IMD and high performance PA design
ii) RF-front end system design: GaN PA and LNA, RF-voltage controlled oscillator, RF-voltage converter
Project description: The goals of the project is creating the state-of-the-art III-V devices on silicon and using that progress to combine III-V devices with silicon CMOS in a monolithic process flow targeting next-generation RF-systems for smart traffic management. Conventional Si-devices cannot provide the range of power and frequency for 5G D2D communication applications. The materials explored are GaN, GaAsP/InGaP, and InGaAs HEMTs as well as LEDs built in those same materials systems. Three key challenges are solved in this project:
i) Innovative device design for record RF-performance: By taking into account the end-system level requirements, high-linearity RF devices are built on GaN platform that employ gm-compensation via threshold voltage engineering to reduce harmonic and IMD content and yield high linearity performance for RF applications.
ii) Device modeling and PDK development: The modeling work involves detailed device characterization, model development and extraction for both GaN and InGaAs based HEMTs. Several modeling challenges such as large-signal modeling for power amplifiers, noise characterization (RF and flicker) for low noise amplifiers, charge-trapping effects in GaN devices and impact ionization effects in InGaAs devices are accomplished. DC, AC, small and large signal, loadpull, AM-AM/AM-PM, RF-noise and phase noise characterization are carried out. Finally custom PDKs are developed to support circuit design that allow DRC, LVS-layout and tapeout.
iii) MMIC design: The project involves the design and characterization of novel circuits such as RF-front ends, RF- DC/DC converters, oscillators etc. on commercial foundry platforms.
This project has resulted in several first demonstrations of low form-factor fully-integrated RF-front end MMICs in GaN and device-level linearity enhancement techniques that have been patented.
Research thrust III: Wide-badgap device modeling and reliability aware circuit design for power conversion
Collaborators: Dr. Seungbum Lim, Dr. Sandeep Bahl, Dr. Vijay Krishnamurthy, Texas Instruments
Project description: GaN HEMT based high voltage (HV) switching converters are gaining foothold in the medium voltage (<1000 V) power conversion applications. The superior breakdown voltage, operating frequency, and high temperature performance of GaN HEMTs enable improved conversion efficiency and smaller footprint of the converters. In order to design such high voltage GaN circuits, the device compact model must accurately describe static and dynamic switching behavior to enable designers to gain insight into the impact of the behavioral nuances of the GaN HEMTs on HV circuit performance, such as non-quasi-statics, which is not possible with available models. The MIT Virtual Source GaNFET (MVSG) model is validated against DC-IV, -CV, and pulsed-IV measurements of fabricated devices as shown and is then verified by comparing measured and simulated signals in a commercial buck converter. This work is the first demonstration of a physics-based GaN HEMT compact model that is calibrated and verified all the way from individual device- to a HV- circuit.
The model with its accurate representation of small and large signal device characteristics for both transport and charge, along with device-heating and field plate depletion behavior (shown in Figure. 1a-1f) can be used for the design of HV-DC-DC converters. The MVSG model is used to study dynamic charge distribution effects in a commercial GaN half-bridge buck converter (EPC9001). The hard-switched transition slew rates (SR) are slower than estimated values from static-device capacitances due to dynamic charge distribution during switching. The dynamic gate-drain capacitance (CGD) is higher during switching causing slower SR and higher switching losses with associated heating as shown in Figure 2a-f. In this work, the physics of carrier charge and transport in a GaN-HEMT is captured using MVSG model and is used as a tool to gain insight into device-circuit interaction effects in a HV-switching circuit.
This work was used in industry-first GaN buck converter product from TI.
Research thrust IV: Industry standard compact model development
Collaborators: CMC industry members: TI, ADI, Raytheon, Toshiba, Qorvo
Project description: The CMC has been the premier standardization organization for compact transistor models since its' inception in 1995. The coalition has standardized ten transistor models, which are the work horses for analogue circuit simulation. The coalition has also standardized API's and netlist languages, as these are needed to efficiently share models among companies. This effort is its' first foray into standardizing a III-V semiconductor transistor model. CMC membership which represents a large portion of the traditional silicon semiconductor industry, formed a sub-committee to start the process of standardizing a GaN HEMT model in 2011. While the silicon semiconductor industry has benefited from standardized models, which are uniformly available across a wide set of EDA tools, the III-V semiconductor industry has largely relied on proprietary models. The technological advantages of GaN HEMTs make the technology attractive to both market segments.
There is a standardization procedure which needs to be followed. First, the committee collects requirements from member companies and the wider industry on what they need to see in a GaN HEMT compact model. These were broadcast to the world in a call for standard model candidates in April 2013. During this first phase, the model candidates were asked to self-evaluate how well their model complies with the requirement list. The committee also reviewed the literature to evaluate the candidate models separately. During the second phase, selected candidates and their sponsor are fitting their model to a common set of hardware data and are asked to ultimately demonstrate how well the model fits the data and show some measures of how well it performed during circuit simulation. The models which are deemed successful, then moved to the third phase in which all members were asked to evaluate the model, according to their requirements and asked to report. In the end, a vote occured to standardize. There are at least two distinct applications for GaN HEMTs, the power-switching and RF applications, which pose different requirements on the model. The committee has chosen MVSG model after it qualified for both application regimes in phase four.
The MVSG model has been chosen as industry standard to support GaN-based product design in industry.
Research thrust V: Emerging device analysis, modeling and design: Steep-subthreshold and 2D-devices
Collaborators: Prof. Max Shulaker, Prof. Asif Khan, Georgia Tech., Prof. Sayeef Salahuddin group, U. C. Berkeley
Project description: There is an increasing need for semiconductor logic devices that can operate at scaled power supply voltage in digital computing systems for the overall energy efficiency in electronics. A fundamental limitation on the scaling of supply voltage in CMOS technology is the Boltzmann limit of 60 mV/decade on the sub-threshold swing (SS) of FETs. Recently the concept of negative capacitance FETs (NCFETs) was proposed to overcome this limitation by using a capacitor with a ferroelectric material (FE-oxide), connected in series with the gate dielectric of a regular MOSFET. The underlying mechanism for sub-60 mV/decade operation of a NCFET is the passive amplification of the gate voltage at the interface between the FE-oxide and the semiconductor channel yielding steep-SS as the ferroelectric negative capacitance (NC) state cancels the equivalent of all the positive capacitances in NCFETs.
The FE-oxide capacitor with Q-V characteristics showing the NC-regime (where dQF/dVF <0) in Figure 1, is connected in series with the gate of a regular MOSFET to constitute the NCFET shown in Figure 1. Simulations are carried out to study the performance of the NCFET by using the MVS-model calibrated against Intel 45-nm NFET which is connected to the FE-oxide capacitor as shown, including the scenario of FE-leakage through RFE. The NCFET model implemented in Verilog-A is called MVSNC model (hosted in NSF-NEEDS website) and can be a useful tool to design NCFET-parameters and evaluate circuit-level performance of NCFETs.
One work on this topic involved the study of impact of dielectric leakage that shifts the Q-V characteristics by Q0, stabilizing the FE-oxide in positive-capacitance (PC) state which has the unintended consequence of decreasing the NCFET performance compared to baseline MOSFETs as shown in Figure 1. Work function engineering (WFE) of the external and internal metal gates was proposed to shift the Q-V characteristics by Voffset as shown in Figure 1 and restores the advantage of leaky-NCFETs in terms of steeper SS by stabilizing the FE-oxide close to the NC-regime (Voffset, Qoffset). Transient simulations of transfer curves of NCFETs for both leaky and non-leaky scenarios in Figure 1 show that NCFETs retain steeper-SS compared to baseline FETs.
Secondly, we collaborated to design optimum FE-oxide capacitances on CNT-FET technology as shown in Figure 2. The fabricated NC-CNTFETs show steeper subthreshold slope and at the same time using MVSNC model, a full system low-power IoT processor was simulated to show performance advancements in terms of 1.7x improvement in energy-delay product.
ii) Steep subthreshold devices: Quantifying the impact of gate efficiency on switching steepness of quantum-well tunnel-FETs
Collaborators: Tao Yu (first author), Prof. Judy Hoyt group MIT
Project description: TFETs with sub-60 mV/dec SS are candidates for future ultra-low power CMOS technology. Various designs for TFETs have been proposed, while sub-60 mV/dec SS is rarely achieved. Dominated by parasitic thermal processes, such as carrier recombination and tunneling-assisted-generation (TAG), most of the previous results showed strong temperature dependence in SS. Weak temperature dependent SS is only recently observed, revealing the true tunneling current steepness. Yet, no methodology has been shown to have universal capability in optimizing the tunneling current steepness due to the unknown internal voltage across the tunneling junction (VTJ). In this work, for the first time, we have studied the experimentally observed temperature independent SS and gate efficiency in InGaAs/GaAsSb QWTFETs with compact modeling and full QM simulation. Gate efficiency of the QWTFETs is extracted and design guidelines are proposed for significant gate efficiency improvements.
DC and RF characterization up to 10 GHz from RT to T = 77 K combined with detailed modeling using MVS framework are used in a comprehensive investigation of the impact of gate efficiency on the subthreshold swing (SS) in Quantum-well Tunnel-FETs (QWTFETs). Calibrated modeling of experimental InGaAs/GaAsSb QWTFETs based on IV, CV and RF measurements and full quantum-mechanical (QM) simulations suggest that only 55% of the gate voltage contributes to the tunneling current modulation which results in degraded switching steepness. This is due to the coupling of the tunneling junction with the MOS structure that severely degrades the gate efficiency. The proposed model can be adapted to analyze the gate efficiency in various TFET designs, and/or to use in circuit simulation. Based on the QM simulations, design guidelines resulting in up to 1.4X improved gate efficiency to ~78% in our device structure are proposed.
Project description: Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, a gate first process technology was used for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, Verilog-A compact models based on the MVS-framework that accurately predict the performance of the fabricated MoS2 FETs as well as a parameterized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools were carried out. Using this CAD flow, combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc−dc converter were designed and fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.